(a) Fields of the Invention
The present invention relates to semiconductor memory devices which include capacitor elements having capacitor insulating films made of a ferroelectric film, and to their fabrication methods.
(b) Description of Related Art
With recent progress in digital technologies, there is a growing trend to rapidly process or store a large capacity of information data. In accordance with this trend, research and development is actively conducted on ferroelectric memory devices employing ferroelectric capacitors with spontaneous polarization properties as capacitor elements constituting the semiconductor memory device.
In order to offer a more improved packing density of the device and resulting increase in the capacity thereof, ferroelectric memory devices including three-dimensional capacitor elements (referred hereinafter to as 3D capacitor elements) are actively developed. In this three-dimensional capacitor element, by three-dimensionally forming the capacitor element over a stepped opening, not only a flat portion but also a side wall portion of the formed element is used for a capacitor. Such a three-dimensionally stacked structure (referred hereinafter to as a 3D stacked structure) is employed to secure, even in a small area, the absolute capacitance necessary for memory operations, so that the cell size can be significantly reduced to attain increases in packing density and capacity.
For the 3D stacked capacitor element as shown above, a contact structure for taking the potential of an upper electrode or a lower electrode of the capacitor element is proposed. In this contact structure proposed, a contact with the upper electrode is connected not from an upper-layer side but from a lower-layer side, specifically, from a conductive layer formed on a semiconductor substrate. However, since in the 3D stacked capacitor element, the relative position of the upper electrode from the substrate becomes high because of its construction, formation of a contact with high aspect ratio is required. For a ferroelectric memory device employing such a capacitor element of a 3D stacked structure, an upper-electrode connection structure in consideration of the yield of such a contact with high aspect ratio (see, for example, Japanese Unexamined Patent Publication No. 2005-268494) is proposed.
Hereinafter, a semiconductor memory device according to the conventional technique mentioned above will be described with reference to the accompanying drawings.
FIG. 7 is a sectional view showing the structure of the conventional semiconductor memory device including a capacitor element of a 3D stacked structure.
Referring to FIG. 7, in a semiconductor substrate 10, a first doped layer 12 and a second doped layer 13 are formed apart from each other with an isolation region 11 interposed therebetween. A first insulating film 14 is formed on the entire surface of the semiconductor substrate 10, and a first hydrogen barrier film 15 is formed on the first insulating film 14. In the first insulating film 14, openings are provided at predetermined positions, respectively, and a first contact plug 16 electrically connected to the first doped layer 12 and a second contact plug 17 electrically connected to the second doped layer 13 are formed in the respective openings.
On the first hydrogen barrier film 15, a first laminated conductive barrier film 18 and a second laminated conductive barrier film 19 having a similar structure to the first laminated conductive barrier film 18 are formed to cover the first contact plug 16 and the second contact plug 17, respectively. A second insulating film 20 covering the first laminated conductive barrier film 18 and the second laminated conductive barrier film 19 is formed with a first opening 21 exposing the top surface of the first laminated conductive barrier film 18 and a second opening 22 exposing the top surface of the second laminated conductive barrier film 19.
The inside of the first opening 21 is formed with a capacitor element composed of a lower electrode 23, a capacitor insulating film 24 made of a ferroelectric film, and an upper electrode 25. The upper electrode 25 is also formed within the second opening 22.
On the upper electrode 25, a third insulating film 26 is formed to expand over the entire surface, and a second hydrogen barrier film 27 is formed on the third insulating film 26. A fourth insulating film 28 is formed on the second hydrogen barrier film 27.
As shown above, the potential of the upper electrode 25 of the capacitor element is indirectly connected to the second doped layer 13 through the second contact plug 17 and the second laminated conductive barrier film 19. Therefore, this structure can relieve the difficulty in forming the contact in the state of high aspect ratio.